Magnetic memories, particularly magnetic random access memories (MRAMs), have drawn increasing interest due to their potential for high read/write speed, excellent endurance, non-volatility and low power consumption during operation. An MRAM can store information utilizing magnetic materials as an information recording medium. One type of MRAM is a spin transfer torque random access memory (STT-RAM). STT-RAM utilizes magnetic junctions written at least in part by a current driven through the magnetic junction. For example, FIG. 1 illustrates a conventional magnetic tunneling junction (MTJ) 10 and its use in a conventional STT-RAM. The conventional MTJ 10 includes a top electrode contact (TEC) 12 which can be part of or in electrical contact with a bit line, an optional top reference layer 14, a free layer 16, and a bottom reference layer 18, as well as a spin orbit active (SO) line 19.
The TEC 12 is a conventional conductive line or electrode. The top reference layer 14 and bottom reference layer 18 are conventional MTJ magnetic reference layers, where both the top reference layer 14 and the bottom reference layer 18 have a magnetization (magnetic moment) that is fixed, or pinned, in a particular direction, typically by an exchange-bias interaction with one or more conventional antiferromagnetic layers (not shown).
The free layer 16 is a conventional MTJ free layer whose magnetic moment can be changed. To switch the magnetization or magnetic moment of the conventional free layer 20, a current is driven through the stack of the MTJ 10. The current carriers are spin polarized and exert a torque on the magnetization of the conventional free layer 16 as the current carriers pass through the conventional free layer 16. When a sufficient current is driven through the MTJ 10, the resulting torque will switch the magnetization direction according to the direction of the current. The differences in magnetic configurations correspond to different magnetoresistances and thus different logical states (e.g. a logical “0” and a logical “1”) of the conventional MTJ 10.
In applications such as STT-RAM, memory cells including conventional magnetic junctions 10 are selected. Typically, this is accomplished by configuring each memory cell to include both the conventional MTJ 10 and a selection transistor (not shown in FIG. 1). When the transistor is turned on, for example by a voltage applied to the transistor's gate, current can be driven through the conventional dual MTJ 10. This current can be a read current or a write current for STT writing. Data may thus be written to or read from the conventional MTJ 10.
In a conventional read operation, read current Iread is passed through the MTJ 10 as shown, and a separate sense-amp compares this read current with the current Iref flowing through a reference cell. If Iread<Iref, then the MTJ 10 is in a high-R state relative to the reference cell, corresponding to, for example, logical “0”. Alternatively, when Iread>Iref, the MTJ 10 is in a low-R state relative to the reference cell, corresponding to a logical “1”.
However, this conventional read operation requires a tight distribution of the resistances in the high and low states. Variations in the fabrication process of the transistor and MTJ, as well as different lead resistances across the chip, can cause overlap of the high and low states for the MTJ array, leading to a read error. One solution to this problem is to add a separate reference cell near each memory MTJ, but this leads to additional memory complexity, and reduced memory chip density. Efforts thus exist to perform read operations in MRAM cells without need for a reference cell.